MAX1184ECM+TD【PDF 5/21 页】IC ADC 10BIT 20MSPS DL 48-TQFP

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MAX1184

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________

Clock Input (CLK)

The MAX1184’s CLK input accepts CMOS-compatible

clock signals. Since the interstage conversion of the

device depends on the repeatability of the rising and

falling edges of the external clock, use a clock with low

jitter and fast rise and fall times (< 2ns). In particular,

sampling occurs on the rising edge of the clock signal,

requiring this edge to provide lowest possible jitter. Any

significant aperture jitter would limit the SNR perfor-

mance of the on-chip ADCs as follows:

where fIN represents the analog input frequency and tAJ

is the time of the aperture jitter.

Clock jitter is especially critical for undersampling

applications. The clock input should always be consid-

ered as an analog input and routed away from any ana-

log input or other digital signal lines.

The MAX1184 clock input operates with a voltage thresh-

old set to VDD/2. Clock inputs with a duty cycle other than

50%, must meet the specifications for high and low peri-

ods as stated in the Electrical Characteristics.

System Timing Requirements

Figure 3 depicts the relationship between the clock

input, analog input, and data output. The MAX1184

samples at the rising edge of the input clock. Output

data for channels A and B is valid on the next rising

edge of the input clock. The output data has an internal

latency of five clock cycles. Figure 4 also determines

the relationship between the input clock parameters

and the valid output data on channels A and B.

Digital Output Data, Output Data Format

Selection (T/B), Output Enable (

OE)

All digital outputs, D0A–D9A (Channel A) and

D0B–D9B (Channel B), are TTL/CMOS logic-compati-

ble. There is a five-clock-cycle latency between any

particular sample and its corresponding output data.

SNR

=×

××

log

)

N - 6

N - 5

N + 1

N - 4

N + 2

N - 3

N + 3

N - 2

N + 4

N - 1

N + 5

N + 6

N + 1

5-CLOCK-CYCLE LATENCY

ANALOG INPUT

CLOCK INPUT

DATA OUTPUT

D9A–D0A

tDO

tCH

tCL

N - 6

N - 5

N - 4

N - 3

N - 2

N - 1

N + 1

DATA OUTPUT

D9B–D0B

Figure 3. System Timing Diagram

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